Conventionally, there is a system which includes a central processing unit (hereinafter referred to as a CPU), a peripheral device such as an image display device and a system memory, all of which are coupled to a bus. In such a system, a bus arbiter is provided for controlling the right to use the bus.
Referring to FIG. 1, there is illustrated a conventional system which includes a peripheral device 1 and a CPU 2, each of which serves as a bus master. The CPU 2 is connected to a bus 5, and the peripheral device 1 is connected to the bus 5 through a buffer 4. A system memory 3 of large size is connected to the bus 5. The system memory 3 functions as a working memory for the CPU 2 and stores data and commands which are supplied to the peripheral device 1. A bus arbiter 6 receives a request for acquiring the right to use the bus 5, which is generated by the peripheral device 1, and controls competition of requests for acquiring the right to use the bus 5 which are generated by the peripheral device 1 and the CPU 2. When the peripheral device 1 needs a command or data stored in the system memory 3, it sends a request signal REQ to the bus arbiter 6. In response to the request signal REQ, the bus arbiter 6 sends the CPU 2 a hold request signal HREQ. When the CPU 2 can transfer the right to use the bus 5 to the peripheral device 1, the CPU 2 returns a hold acknowledge signal HACK to the bus arbiter 6. In response to the hold acknowledge signal HACK, the bus arbiter 6 sends an acknowledge signal ACK to the peripheral device 1. At the same time, the bus arbiter 6 outputs a gate signal to the buffer 4 so as to turn 0N the buffer 4 whereby the peripheral device 1 can be connected to the bus 5. Then the peripheral device 1 obtains a command or data stored in the system memory 3 through the bus 5 and the buffer 4. When the peripheral device 1 inputs a command or data from the CPU 2, the system operates in the same manner.
However, the conventional system has disadvantages described below. When the peripheral device 1 such as an image display device needs data such as image data stored in the system memory 3, the peripheral device 1 acquires the right to use the bus 5, and reads out image data from the system memory 3. Normally, a large amount of image data (in a unit of kilo-words to mega-words) is successively read out and then input in the peripheral device 1 at one time. Therefore, efficiency in using the CPU 2 and the bus 5 is high.
On the other hand, when the peripheral device 1 needs a command, which is to be supplied from the system memory 3 or the CPU 2, the peripheral device 1 acquires the right to use the bus 5 and inputs a small amount of data related to the command (equal to a few words, for example). When the command has been input in the peripheral device 1, the peripheral device 1 releases the bus 5 from the exclusive use. When a next command is needed, the peripheral device 1 acquires the right to use the bus 5 again and inputs a small amount of data. Thereafter, the peripheral device 1 releases the bus 5 again. Each time the peripheral device 1 acquires the right to use the bus 5, the CPU 2 must interrupt operation. Thus, efficiency in using the CPU 2 and the bus 5 is low.